1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a storage circuit which stores, e.g., the security data of a digital product, code data, ID data unique to a chip, trimming data for timing adjustment or voltage regulation of an internal circuit in a nonvolatile manner by using fuse elements.
2. Description of the Related Art
Several techniques are known for implementing a storage circuit which stores data in a nonvolatile manner in a semiconductor device. For example, when a large storage capacity is necessary, and repeated rewrites are required, a flash memory having memory cells with a stacked gate structure is formed. In this case, a special process different from a standard CMOS process is necessary. For, e.g., a memory LSI which mainly stores data in a nonvolatile manner, the cost overhead for the use of the special process can be suppressed by increasing the capacity.
In a system LSI or the like, however, the cost overhead increases when the dedicated process is used only to store small-capacity data such as security data, code data, ID data unique to a chip, or trimming data in a nonvolatile manner. In addition, the number of rewrites need not be 100,000, unlike a flash memory, although it depends on the application purpose. If semi-permanent data which may be written as needed should be stored in a nonvolatile manner, the number of rewrites needs to be only several times. It is not sensible to use the expensive flash process to guarantee 100,000 rewrites for such an application purpose. In this case, it is preferable to use a nonvolatile memory element which can be formed by the standard CMOS process.
As a nonvolatile memory element which can be implemented by the standard CMOS process, a fuse element is widely known (e.g., Jpn Pat. Appln. KOKAI Publication Nos. 2002-76126 and 2002-368096). As a fuse element, generally, a type whereby data is programmed by means of a laser beam or a type (electrical-fuse or e-fuse) whereby data is electrically programmed is used.
The former uses a metal or polysilicon interconnection as a fuse element. Programming is carried out by fusing the interconnection by irradiating it with a laser beam.
Conversely, the latter uses, e.g., an oxide film serving as an insulating member as a fuse element. To program data, high-voltage stress is applied to destroy the oxide film and cause the fuse element to conduct. That is, data is stored in accordance with the connection/disconnection of the oxide film. Alternatively, a polysilicon interconnection having a silicide layer formed on its surface by a salicide process is used as a fuse element. A high voltage is applied to supply a current to the silicide layer and destroy it. Accordingly, the resistance greatly increases. Data is stored in accordance with the change in resistance.
The fuse element whereby data is programmed by means of a laser beam must be programmed in a wafer state. However, the fuse element whereby data is electrically programmed can be programmed even after it is packaged or assembled in a system. Hence, code data or ID data unique to a chip can be programmed in the wafer state. In addition, even after assembly, the user can program security data or trimming data for timing adjustment or voltage regulation.
FIG. 1 is a block diagram showing the arrangement of a conventional storage circuit which uses the above-described electrically programmable fuse element. This storage circuit comprises a “1+n”-bit write data latch group 11, a “1+n”-bit fuse circuit group 12, and a “1+n”-bit read data latch group 13. One bit of each of the write data latch group 11, fuse circuit group 12, and read data latch group 13 stores an activation signal (enable bit data) En which represents activation of the storage circuit. The remaining n bits store data D1, D2, . . . , Dn such as code data, ID data unique to the chip, security data, and trimming data.
The data D1, D2, . . . , Dn to be stored in the fuse circuit group 12 is externally input as input signals Din1, Din2, . . . , Dinn or generated by an internal circuit in the semiconductor device and latched by the write data latch group 11. In accordance with the data D1, D2, . . . , Dn latched by the write data latch group 11, a high voltage is selectively applied across each fuse element in the fuse circuit group 12.
Accordingly, data is selectively written in accordance with the destruction/nondestruction state of each fuse element.
To use the data stored in the fuse circuit group 12, the data must be converted into digital signals. To do this, when, e.g., the storage circuit is powered on, the data is read out in an analog manner in accordance with the destruction/nondestruction state of each fuse element in the fuse circuit group 12.
The results are latched by the read data latch group 13 prepared for the fuse elements. With this operation, while the storage circuit is powered on, the nonvolatile fuse data can be used as a digital signal latched by the read data latch group 13. This data is output onto a fuse data bus 14 and controls the internal circuits or is output to an external device.
FIG. 2 is a circuit diagram showing detailed arrangements of a write data latch 11i, fuse circuit 12i, and read data latch 13i corresponding to the ith bit (i=1, 2, . . . , n) in the circuit shown in FIG. 1. The write data latch 11i includes clocked inverters 20 and 21, an inverter 22, a NOR gate 23, and a MOSFET 24. Input data Dini corresponding to the ith bit is supplied to the input terminal of the clocked inverter 20. The input terminal of the clocked inverter 21 and the output terminal of the inverter 22 are connected to the output terminal of the clocked inverter 20. The input terminal of the inverter 22 and one input terminal of the NOR gate 23 are connected to the output terminal of the clocked inverter 21. A program signal /PROGRAM is supplied to the other input terminal of the NOR gate 23. The output terminal of the NOR gate 23 is connected to the gate of the MOSFET 24. One end of the current path of the MOSFET 24 is connected to the fuse circuit 12i. The other end of the current path is connected to a ground point Vss.
The fuse circuit 12i includes a fuse element 25 and a MOSFET 26. One terminal of the fuse element 25 is connected to a high-voltage power supply Vpp. The other terminal of the fuse element 25 is connected to one end of the current path of the MOSFET 26. The other end of the current path of the MOSFET 26 is connected to one end of the current path of the MOSFET 24.
The read data latch 13i includes MOSFETs 27 and 28, clocked inverters 29 and 30, and inverters 31, 32, and 33. The one end of the current path of the MOSFET 27 is connected to one end of the current path of the MOSFET 26. The other end of the current path of the MOSFET 27 is connected to one end of the current path of the MOSFET 28. The gate of the MOSFET 27 is connected to a power supply Vcc. The other end of the current path of the MOSFET 28 is connected to the ground point Vss. A reset signal RESET is supplied to the gate of the MOSFET 28. The input terminal of the clocked inverter 29 is connected to the connection point between the current paths of the MOSFETs 27 and 28. The input terminal of the clocked inverter 30 and the output terminal of the inverter 31 are connected to the output terminal of the clocked inverter 29. The input terminals of the inverters 31 and 32 are connected to the output terminal of the clocked inverter 30. The input terminal of the inverter 33 is connected to the output terminal of the inverter 32. Read data Douti is obtained from the output terminal of the inverter 33.
In the above arrangement, data programming is done in the following way. In the example to be described below, the fuse element 25 is of an insulating film destruction type which destroys an insulating film to set a conductive state. When the input data Dini is set to the “L” level, and the program signal /PROGRAM is set to the “L” level, the output from the NOR gate 23 changes to the “H” level. In this state, a selection signal SELECT is set to the “H” level. Accordingly, the MOSFETs 24 and 26 are turned on to supply a current from the high-voltage power supply Vpp to the ground point Vss through the fuse element 25 and the current paths of the MOSFETs 26 and 24. Then, the insulating film of the fuse element 25 is destroyed to render the fuse element 25 conductive.
The conductive state of the fuse element 25 is latched by the read data latch 13i as stored data. More specifically, when the reset signal RESET temporarily changes to the “H” level, the MOSFET 28 is turned on. The input terminal of the clocked inverter 29 is discharged and set to the “L” level. Accordingly, the output from the clocked inverter 29 changes to the “H” level. This state is latched by the clocked inverters 29 and 30 and inverter 31 and set as an initial state. When the fuse element 25 is being rendered conductive, and the reset signal RESET returns to the “L” level, the input terminal of the clocked inverter 29 is charged from the high-voltage power supply Vpp through the current path of the MOSFET 27 and set to the “H” level. The output from the clocked inverter 29 changes to the “L” level. This state is latched by the clocked inverters 29 and 30 and inverter 31. When the fuse element 25 is not being rendered conductive, the initial state is maintained.
The fuse element 25 stores data by using an irreversible destruction phenomenon in an oxide film or electrode material regardless of whether the fuse element is of an insulating film destruction type which destroys, e.g., an oxide film, or a conductive film destruction type which destroys, e.g., a silicide layer. For this reason, once the fuse element is programmed, it cannot be returned to the nondestruction state as before. Hence, a rewrite cannot be executed at all, although it is very advantageous that a nonvolatile storage circuit can be formed by using the standard CMOS process.